1. Field of the Invention
The present invention relates to an analog switch circuit and a sample-and-hold circuit including the analog switch circuit.
2. Description of the Related Art
A sample-and-hold circuit has been widely used for Analog-to-Digital Converters (ADCs), etc. The sample-and-hold circuit is realized by combining analog switch circuits and capacitors. In order to improve conversion accuracy of the ADCs using the analog switch circuits, the following requirements are given. According to one requirement, a resistance value (on resistance) Ron when an analog switch turns on must be sufficiently small. According to another requirement, a resistance value (off resistance) Roff when the analog switch turns off must be sufficiently large, or the off leakage current Ioff must be sufficiently small.
The analog switch circuit is constituted by MOS transistors. The on resistance Ron and off resistance Roff of the MOS transistors are determined by the device dimensions of the MOS transistors that have been made by a specific process. More specifically, on resistance Ron is determined in accordance with the difference between gate-source voltage Vgs when the MOS transistor drives on and threshold voltage Vth. On the other hand, off resistance Roff is determined in accordance with the difference between the gate-source voltage Vgs when the MOS transistor drives off and the threshold voltage Vth.
Scale-down of devices included in a large-scale semiconductor integrated circuit (LSI) are advanced ones. The power supply voltage supplied to the analog switch circuit therefore drops. Hence, the gate-source voltage Vgs of the MOS transistor used as a switch device (element) also drops, too. As a result, the on resistance Ron increases. In this case, the threshold voltage Vth of the MOS transistor can be made low, whereby on resistance Ron is reduced. Nonetheless, the off resistance Roff decreases.
When the threshold voltage Vth of the MOS transistor is set to a predetermined value, the off resistance Roff depends on the gate-source voltage Vgs. The off leakage current Ioff is given by Ioff=Vds/Roff. In this case, Vds is a drain-source voltage. Thus, the off leakage current Ioff of the MOS transistor depends on each of gate voltage Vg, drain voltage Vd and source voltage Vs. In most cases, the gate voltage Vg for driving off the MOS transistor is at an “L” level (VSS) in the NMOS transistor and at an “H” level (VDD) in the PMOS transistor. As long as the NMOS transistor and the PMOS transistor remain off, the gate voltage Vg has a constant value in the NMOS and PMOS transistors. Therefore, the off leakage current Ioff of either MOS transistor depends on the drain voltage and the source voltage. Usually, the input signal is supplied as drain potential or source potential. An off leakage current that depends on the input-signal potential is generated in the MOS transistor of the analog switch circuit.
“Design of Analog CMOS integrated Circuits, Behzad Razavi, McGRAW-HILL, 2001, (page 425, FIG. 12.30)” discloses that a sample-and-hold circuit using an analog switch circuit and an operational amplifier. In general, when a leakage current is flowed in the analog switch circuit which is inserted between an inverting input terminal of the operational amplifier and an output terminal thereof, a value of the leakage current is dependent on a hold voltage of the sample-and-hold circuit. As a result, distortion occurs in the hold voltage.
JPN. PAT. APPLN. KOKAI Publication No. 8-213909 discloses that a potential difference between input and output of a switch device is set to zero. U.S. patent application Ser. No. 6,359,496 discloses the following technique. According to the technique, first and second switch circuits are connected in parallel in order to reduce the influence caused by the off leakage current of a switch device. The first switch circuit is composed of an NMOS transistor having a larger threshold voltage and a PMOS transistor, which are connected in parallel. The second switch circuit is composed of two NMOS transistors having a smaller threshold voltage and one PMOS transistor, which are connected in serial. In this case, transistors having two kinds of threshold voltages are required.